1. Technical Field
The present invention relates generally to micro-electromechanical systems (MEMS) and, more specifically, to a system and method for relieving stress and optimizing heat management in a three dimensional (3D) chip stack.
2. Introduction
As consumer demand increases for smaller multi-function devices, manufacturers face significant challenges to integrate different semiconductor technologies on a single die. Multichip packages such as, for example, 3D chip stacks, have become increasingly popular to increase device density and to combine traditionally incompatible technologies, such as logic, analog, memory, and MEMS. One of the major challenges facing multichip packages is stress applied to its components. One element contributing to the stress of the components is packaging designs implementing a fixed-distance chip stack. The stress resulting from the fixed-distance chip stack may warp the components and may even cause physical damage to the chip stack. Many conventional multichip package designs have attempted to alleviate stress by implementing a mechanically flexible interconnection (MFI) such as, for example, using a through silicon via (TSV). However, known MFIs are required to maintain a constant vertical alignment between chips to maintain electrical connection and provide stress relief. However, due to this alignment restriction, known MFIs only relieve stress in a vertical direction and are susceptible to loss of connection as a result of cross-directional, horizontal movement between the chips.
Another adverse condition facing the components of a multichip package is heat generated through use of the multichip package. Heat generated in chip stacks is known to cause the multichip package to malfunction. As such, heat management may be implemented to alleviate the heat in the chip stack. However, known methods of heat management such as, for example, thermal throttling, respond to the detection of an overheating chip stack by reducing the power to the chip stack or reducing the speed at which the chip stack is running Accordingly, current methods of heat management limit the performance of the chip stack and are, therefore, undesirable.